The present invention relates to computing techniques. More particularly, the present invention provides a plurality of memory devices configured with a memory controller using a common interface bus having multiple signals. In other examples where a memory controller controls multiple memory devices, interface devices are often deployed to improve the quality of the signal transmissions between the memory controller and the memory devices. As an example, DDR3, and DDR4 Registered memory modules use one or more registers to buffer and re-drive the command, control and address signals from the host memory controller to multiple DDR3 and DDR4 SDRAM devices. DDR3, and DDR4 Load Reduction DIMM memory modules use memory buffer to buffer and re-drive the data, command, control and address signals from the host memory controller to multiple DDR3 and DDR4 SDRAM devices.
High-speed digital signals, such as the data, clock and control signals that are conveyed between a host controller and a memory module, are typically received by a respective receiver circuits. The host controller often couples to a memory controller, which is configured with multiple dual inline memory modules, commonly called “DIMMs,” via a common interface. As the signals become faster, signal integrity becomes more important, and more difficult to operate and monitor efficiently.
From the above, it is seen that techniques for improving memory module devices and methods of use are highly desirable.